Compact RIO Controllers
Composition of CRIO PAC
Compact RIO is industrial ruggedized Programmable Automation Controller PAC that provides interface to C Series Module for I/O connectivity. Certain models carry Field Programmable Gate Array in the back plate chassis. 
A full Compact RIO PAC controller could be a combination of and FPGA Chassis with hot-swappable C Series modules and a pluggable real time controller that provide interface to all I/O available from a standard PC i.e HDMI, USB, Wifi, RJ45 and so on. These real time controllers also come pre-installed with real time OS or even windows OS.
LabVIEW FPGA DRAM Applications
In this article, I wanted to briefly discuss how FPGA DRAM memory could be used in LabVIEW FPGA vi. There are many benefits of using FPGA DRAM in high performance computing application that requires huge bandwidth. National Instruments FPGA products could out-perform PCI-Express, for instance PXIe-7976 which has a single DRAM bank that could offer up to 10.5GB/s. However, it is essential to use high-bandwidth benefit of DRAM carefully and it must be noted that DRAM high bandwidth might not necessarily provide high latency.
Bandwidth, Clock rate, Access type for DRAM read/write
Access type
Almost all FPGA specifications and product sheets would provide information on Access type and bandwidth. For maximum throughput, size of data type should match access size of device. For instance cRIO-903x has access size of 128 bits which is 16 bytes. It is however good programming practice to cluster data to make up to 16 bytes prior storage. As leave bytes empty on every write would mean remaining bits in access size would still be written by some unknown value. We lose space as well as bandwidth by not utilizing full access size.
Clock rate and Bandwidth
Clock rate of cRIO-903x is 100 MHz so it could write 100M points in 1 seconds and if our point is made up of 16 bytes as above. Then we are transmitting 100M multiply 16 = 1.6GB/s.
High Bandwidth but low latency
High bandwidth is good as we get large amount of data every time we access DRAM. Latency is ‘delay’ between read request and read receive. Due to highly pipelined architecture of DRAM, there is a large amount of latency between request and actual execution of request. I would always recommend using best programming techniques to make most of DRAM functions. Labview FPGA Memory Write and Read functions also come with inputs such as ‘Input/Output Valid’ and ‘Ready for Input/Output’. Such I/O could be used to make access to DRAM appropriately.
Application of Labview FPGA DRAM Bandwidth
DRAM memory storage is useful in applications where we want to push and pull big chunk of data on a single access and could easily with a short delay of DRAM latency. The applications of high bandwidth are ever so increasing. From the requirement of achieving high throughput imaging and analysis applications to quantum computing as well as innovative usage in remote visualization and internet application, engineering innovation has often benefitted from data gathered at high bandwidth rate.
